First, an integrated circuit which is a target of the power supply noise evaluation will be described. FIG. 10 is a circuit diagram illustrating an example of an integrated circuit. The integrated circuit of FIG. 10 includes power supply wiring sections 101a and 101b and a logic circuit section 102. The power supply wiring section 101a is a power supply wiring that connects an externally given potential VDD and a VDD terminal of the logic circuit section 102. The power supply wiring section 101b is a power supply wiring that connects an externally given potential VSS and a VSS terminal of the logic circuit section 102. Conventionally, as an evaluation method of a power supply system in such an integrated circuit, the following two evaluation methods have been used.
The first evaluation method creates a simulation model for the entire integrated circuit without distinguishing between the power supply wiring section and logic circuit section and performs simulation of operation of the entire integrated circuit to thereby measure a power supply waveform. FIG. 11 is a circuit diagram illustrating an example of a simulation model in the conventional first evaluation method. The simulation model of FIG. 11 includes power supply wiring section 111a and 111b and a logic circuit section 112. The power supply wiring sections 111a and 111b and the logic circuit section 112 correspond respectively to the abovementioned power supply wiring sections 101a and 101b and logic circuit section 102. The first evaluation method uses such an entire simulation model to perform a single simulation.
The second evaluation method creates a simulation model individually for the logic circuit section and power supply wiring section and separately performs simulation of operation of the logic circuit section and that of the power supply wiring section. FIG. 12 is a circuit diagram illustrating an example of a logic circuit section model in the conventional second evaluation method. FIG. 13 is a circuit diagram illustrating an example of a power supply wiring section model in the conventional second evaluation method. In FIGS. 12 and 13, the same reference numerals as those in FIG. 11 denote the same or corresponding parts as those in FIG. 11, and the descriptions thereof will be omitted here. In the second evaluation method, a logic circuit section model and a power supply wiring section model are created as simulation models. The logic circuit section model includes a logic circuit section 112. The power supply wiring section model includes power supply wiring sections 111a and 111b and a current source 124. A power is supplied to the logic circuit section 112 by an ideal source.
The second evaluation method uses the ideal source to be given to the logic circuit section 112 to perform simulation of the logic circuit section model to thereby measure a current waveform of a power supply of the logic circuit section 112 and inputs the obtained current waveform to the power supply wiring sections 111a and 111b by means of the current source 124 to perform simulation of the power supply wiring section to thereby measure a voltage change.
As a related art, there is known a voltage drop/current density analysis apparatus that replaces a charging/discharging path by a current source/switch model and replaces a power supply wiring by a resistor model to thereby generate an analysis circuit.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2002-56044
The first evaluation method can sometimes be applied to a case where the circuit scale is small. However, when the circuit scale becomes larger, simulation cannot run or, if simulation runs, a considerably long time is taken for the simulation.
Further, in the second evaluation method, the voltage and current, which correlate with each other in the actual circuit, are measured independently, so that an evaluation result does not coincide with the actual operation. As a result, an effective evaluation cannot sometimes be obtained.